The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI (semiconductor on insulator) technology for minimizing short-channel effects and for maximizing drive current for the field effect transistor having scaled down dimensions of tens of nanometers.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension 104 and a source extension 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension 104 and the source extension 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate electrode 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate electrode 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where the MOSFET 100 is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
As the dimensions of the MOSFET 100 are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET 100. Short-channel effects that result due to the short length of the channel between the drain extension 104 and the source extension 106 of the MOSFET 100 are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET 100 become difficult to control with bias on the gate electrode 118 with short-channel effects which may severely degrade the performance of the MOSFET.
Referring to FIG. 2, to enhance the control of electrical characteristics of a MOSFET 200, a three-sided gate electrode 202 is formed to surround a pillar 204 of semiconductor material for the MOSFET 200 formed with SOI (semiconductor on insulator) technology. FIG. 3 shows the cross sectional view of the three-sided gate electrode 202 across line Axe2x80x94A in FIG. 2. The pillar 204 of semiconductor material is formed on a layer of buried insulating material 206 on a semiconductor substrate 208 in SOI (semiconductor on insulator) technology, as known to one of ordinary skill in the art of integrated circuit fabrication. Typically, the semiconductor substrate 208 and the pillar 204 are comprised of silicon, and the three-sided gate electrode 202 is comprised of polysilicon. In addition, the layer of buried insulating material 206 is comprised of silicon dioxide (SiO2).
A three-sided gate dielectric 210 is formed between the pillar 204 and the three sided gate electrode 202. The three-sided gate dielectric 210 is comprised of one of silicon dioxide (SiO2), silicon nitride (Si3N4), or a dielectric material such as a metal oxide with a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO2).
Referring to FIG. 2, a drain and source dopant is implanted into the pillar 204 at a first side of the three-sided gate electrode 202 to form a drain 212 of the MOSFET 200 and at a second side of the three-sided gate electrode 202 to form a source 214 of the MOSFET 200. A drain contact pad 216 is formed to provide connection to the drain 212 of the MOSFET 200, and a source contact pad 218 is formed to provide connection to the source 214 of the MOSFET 200.
Referring to FIGS. 2 and 3, the channel region of the MOSFET 200 is the gate length of the pillar 204 between the drain 212 and the source 214 and covered by the three-sided gate electrode 202. Because charge accumulation within such a channel region is controlled by bias on the gate electrode 202 on three surfaces of the pillar (instead of just the one top surface of the semiconductor substrate 102 in the conventional MOSFET of FIG. 1), electrical characteristics of the MOSFET 200 formed with SOI technology is more controllable to compensate for short-channel effects of the MOSFET 200.
However, the effective drive current width of the MOSFET 200 may be limited. FIG. 4 shows the cross-sectional view of the pillar 204 of FIG. 3 with the pillar 204 and the gate dielectric 210 enlarged. The drain to source current of the MOSFET 200 is proportional to the effective drive current width of the MOSFET 200. Referring to FIG. 4, the effective drive current width of the MOSFET 200 is the total perimeter distance of the gate dielectric 210 surrounding the pillar 204 including the height 220 of the pillar 204 for the first and second sides of the pillar 204 and the width 222 of the pillar 204 for the top surface of the pillar 204. If xe2x80x9cHxe2x80x9d denotes the height 220 of the pillar 204 and xe2x80x9cWxe2x80x9d denotes the width 222 of the pillar 204, then the effective drive current width xe2x80x9cWeffxe2x80x9d of the MOSFET 200 is as follows:
Weff=W+2xH
However, as the dimensions of the MOSFET 200 are scaled down for a smaller gate length of the pillar 204 from the drain contact 216 to the source contact 218, etching processes have aspect ratio limitations such that the height 220 of the pillar 204 is limited, as known to one of ordinary skill in the art of integrated circuit fabrication. With a limited height 220 of the pillar 204, the effective drive current width, Weff, and in turn the speed performance of the MOSFET 200 are disadvantageously limited.
Nevertheless, fabrication of the MOSFET 200 in SOI (semiconductor on insulator) technology with formation of the three-dimensional pillar 204 having gate bias at a plurality of sides of the pillar 204 is desirable for minimizing undesired short-channel effects. Thus, a mechanism is desired for maximizing the effective drive current of a MOSFET formed with the three-dimensional pillar having gate bias at a plurality of sides of the pillar 204 in SOI (semiconductor on insulator) technology.
Accordingly, in a general aspect of the present invention, a pillar of semiconductor material is formed to have an upside down T-shape to maximize the effective drive current of a MOSFET. With such an upside down T-shape of the pillar, any point of a cross-section of such a pillar is more closely located to the gate bias applied at a surface of such a pillar such that the effective drive current of the MOSFET is maximized.
In one embodiment of the present invention, for fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second side surfaces, and the pillar has a width, a length, and a height. A masking structure is formed on a center portion of the top surface of the pillar along the length of the pillar. A top portion of the height of the pillar is etched from exposed surfaces of the top surface of the pillar down to a bottom portion of the height of the pillar to form an upside down T-shape for the pillar. A gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar for a gate length along the length of the pillar. A gate electrode material is deposited on the gate dielectric material to surround the pillar for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar.
In this manner, the gate dielectric material contacts more numerous surfaces of the semiconductor pillar. For a given height and width of the semiconductor pillar, any point of a cross-section of such a pillar is more closely located to the gate bias applied at a surface of such a pillar such that the effective drive current of the field effect transistor is maximized. In addition, since gate bias on the gate electrode is applied on the more numerous surfaces of the semiconductor pillar, the short-channel effects of the field effect transistor are minimized.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.